Embodiments of the present invention relate to a nonvolatile memory device and a method of verifying the same and, more particularly, to a nonvolatile memory device and a method of verifying the same, which perform a stabilized verification operation.
In recent years, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific time intervals. To develop a high capacity of a memory device capable of storing a large amount of data, technology for a high degree of integration of memory cells is being developed.
For the high degree of integration of memory cells, a NAND type flash memory device in which a number of memory cells are coupled in series to form one cell string and two cell strings share one contact has been developed. In such a NAND type flash memory device, program and erase operations are performed by controlling the threshold voltage of a memory cell while injecting or discharging electrons into or from a floating gate according to F-N tunneling.
Accordingly, an erased memory cell has a negative threshold voltage because electrons are discharged from a floating gate. A programmed memory cell has a positive threshold voltage because electrons are injected into a floating gate. However, the NAND type flash memory device has defects resulting from a charge gain or a loss of charges, and so several verification operations are performed on the memory device in relation to such characteristics. A page buffer is used to verify whether the program and erase operations have been properly performed.
A verification method using a known page buffer is performed by precharging the bit line of a memory cell array, coupled to the page buffer, to a high level voltage for a set period of time and then supplying a verification voltage to the word line of a memory cell coupled to the bit line in order to detect the voltage level of the corresponding bit line.
Recently, to further increase the degree of integration of the memory cells, active research is being carried out on a multi-bit cell which is capable of storing plural data in one memory cell. This type of a memory cell is called a multi-level cell (MLC). A memory cell capable of storing a single bit in one memory cell is called a single level cell (SLC).
The MLC has several distributions of threshold voltages. In such an MLC, a program operation is verified by performing several verification operations. That is, a selected bit line of a corresponding memory cell array is precharged to a high level voltage for a set period of time, and several verification operations are then performed in order to verify whether the voltage level of the bit line has been maintained at a high level or has been discharged to a low level. In this case, a leakage current is generated in the bit line, initially precharged to a high level, because of several verification operations occurring after a passage of time, which can lead to a gradual drop in the voltage level of the bit line. Accordingly, in a subsequent verification operation, a problem can occur in which the corresponding memory cell is verified to have been successfully programmed even though it has not been successfully programmed.